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1 GSPS Direct Digital Synthesizer AD9858
FEATURES
1 GSPS internal clock speed Up to 2 GHz input clock (selectable divide-by-2) Integrated 10-bit D/A converter Phase noise < 145 dBc/Hz @ 1 kHz offset Output frequency = 100 MHz (DAC output) 32-bit programmable frequency register Simplified 8-bit parallel and SPI(R) serial control interface Automatic frequency sweeping capability 4 frequency profiles 3.3 V power supply Power dissipation 2 W typical Integrated programmable charge pump and phase frequency detector with fast lock circuit Isolated charge pump supply up to 5 V Integrated 2 GHz mixer
GENERAL DESCRIPTION
The AD9858 is a direct digital synthesizer (DDS) featuring a 10-bit DAC operating up to 1GSPS. The AD9858 uses advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sine wave at up to 400+ MHz. The AD9858 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). The frequency tuning and control words are loaded into the AD9858 via parallel (8-bit) or serial loading formats. The AD9858 contains an integrated charge pump (CP) and phase frequency detector (PFD) for synthesis applications requiring the combination of a high speed DDS along with phase-locked loop (PLL) functions. An analog mixer is also provided on-chip for applications requiring the combination of a DDS, PLL, and mixer, such as frequency translation loops, tuners, and so on. The AD9858 also features a divide-by-2 on the clock input, allowing the external clock to be as high as 2 GHz. The AD9858 is specified to operate over the extended industrial temperature range of -40C to +85C.
APPLICATIONS
VHF/UHF LO synthesis Tuners Instrumentation Agile clock synthesis Cellular base station hopping synthesizer Radar Sonet/SDH clock synthesis
LO DIV PD CP CPISET FREQUENCY ACCUMULATOR IF
FUNCTIONAL BLOCK DIAGRAM
RF /M /N CHARGE PUMP ANALOG MULTIPLIER PHASE DETECTOR
AD9858
DIGITAL PLL
PHASE ACCUMULATOR DACISET 32 15 15 PHASE-TOAMPLITUDE CONVERSION 10 DAC IOUT IOUT
FREQUENCY ACCUMULATOR RESET
PHASE ACCUMULATOR RESET
DELTA FREQUENCY WORD
DELTA FREQUENCY RAMP RATE
FREQUENCY TUNING WORD
14
PHASE OFFSET ADJUST
DAC CLOCK
32 RESET
32
TIMING AND CONTROL LOGIC
FUD SYNCLK
CONTROL REGISTERS
SYNC
POWERDOWN LOGIC
/8
M U X
/2
REFCLK REFCLK
03166-A-001
PROFILE I/O PORT SELECT (SER/PAR)
Figure 1. Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9858 TABLE OF CONTENTS
Features .......................................................................................... 1 Applications................................................................................... 1 General Description..................................................................... 1 Functional Block Diagram .......................................................... 1 AD9858--Electrical Specifications ................................................ 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration............................................................................. 7 Pin Function Descriptions .............................................................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 15 Overview ..................................................................................... 15 Component Blocks..................................................................... 15 Modes of Operation................................................................... 17 Synchronization.......................................................................... 19 Programming the AD9858........................................................ 21 AD9858 Application Suggestions............................................. 29 Evaluation Boards ...................................................................... 30 Outline Dimensions ....................................................................... 31 Warning ....................................................................................... 31 Ordering Guide .......................................................................... 31
REVISION HISTORY
11/03--Data Sheet Changed from a REV. 0 to a REV. A Changes to SPECIFICATIONS........................................................ 5 Moved ESD Caution to ..................................................................... 6 Moved Pin Configuration to ............................................................ 7 Moved Pin Function Description to ............................................... 8 Changes to Equations........................................................................ 19 Changes to Delta Frequency Ramp Rate Word (DFRRW) .......... 27
Rev. A | Page 2 of 32
AD9858 AD9858--ELECTRICAL SPECIFICATIONS
Table 1. Unless otherwise noted, VDD = 3.3 V 5%, CPVDD = 5 V 5%, RSET = 2 k, CPISET = 2.4 k, Reference Clock Frequency = 1 GHz.
Parameter REF CLOCK INPUT CHARACTERISTICS1, 2 Reference Clock Frequency Range (Divider Off) Reference Clock Frequency Range (Divider On) Duty Cycle @ 1 GHz Input Capacitance Input Impedance Input Sensitivity Temp Full Full 25C 25C 25C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level VI VI V V IV VI Min 10 20 42 Typ Max 1000 2000 58 Unit MHz MHz % pF dBm Bits mA % FS A LSB LSB k V dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
50 3 1500
-20 10 20
+5
DAC OUTPUT CHARACTERISTICS
Resolution Full-Scale Output Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Impedance Voltage Compliance Range Wideband SFDR (DC to Nyquist) 40 MHz FOUT 100 MHz FOUT 180 MHz FOUT 360 MHz FOUT 180 MHz FOUT (700 MHz REFCLK) Narrow-Band SFDR33 40 MHz FOUT (15 MHz) 40 MHz FOUT (1 MHz) 40 MHz FOUT (50 kHz) 100 MHz FOUT (15 MHz) 100 MHz FOUT (1 MHz) 100 MHz FOUT (50 kHz) 180 MHz FOUT (15 MHz) 180 MHz FOUT (1 MHz) 180 MHz FOUT (50 kHz) 360 MHz FOUT (15 MHz) 360 MHz FOUT (1 MHz) 360 MHz FOUT (50 kHz) 180 MHz FOUT (15 MHz) (700 MHz REFCLK) 180 MHz FOUT (1 MHz) (700 MHz REFCLK) 180 MHz FOUT (50 kHz) (700 MHz REFCLK) OUTPUT PHASE NOISE CHARACTERISTICS (@ 103 MHz IOUT) @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset OUTPUT PHASE NOISE CHARACTERISTICS (@ 403 MHz IOUT) @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset 5 -10 40 +10 15 1 1.5 AVDD + 0.5 60 54 53 50 52 82 87 88 81 82 86 74 84 85 75 85 86 65 80 84 -147 -150 -152 -133 -137 -140
VI VI VI VI VI VI V V V V IV V V V V V V V V V V V V V V V V V V V V V
0.5 1 100 AVDD - 1.5
Rev. A | Page 3 of 32
AD9858
Parameter OUTPUT PHASE NOISE CHARACTERISTICS (@ 100 MHz IOUT with 700 MHz REFCLK) @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset PHASE DETECTOR AND CHARGE PUMP Phase Detector Frequency Phase Detector Frequency (Divide-by-4 Enabled)4 Charge Pump Sink and Source Current5 Fast Lock Current (Acquisition Only) Open-Loop Current (Acquisition Only) Sink and Source Current Absolute Accuracy6 Sink and Source Current Matching6 Input Sensitivity PDIN and DIVIN (50 )7 Input Impedence PDIN and DIVIN (Single-Ended) Phase Noise @ 100 MHz Input Frequency @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Charge Pump Output Range8 MIXER IFOUT9 FRF FLO Conversion Gain LO Level RF Level Input IP3 1 dB Input Compression Power10 Input Impedance (Single-Ended) LO RF LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance POWER SUPPLY PDISS (Worst-Case Conditions--Everything on PFD Input Frequency 150 MHz) PDISS (DAC and DDS Core Only Worst-Case) PDISS (Power-Down Mode) PDISS Mixer Only PDISS PFD and CP (@ 100 MHz) Only Temp Test Level Min Typ Max Unit
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
V V V V V V VI VI VI VI VI V V IV V V V V V V VI VI VI VI VI VI VI V V VI VI VI VI V VI VI VI VI VI
-125 -140 -148 -150 -150 -150 150 400 4 7 30 2.5 1 -15 1 110 140 148 CPVDD 400 2 2 0.0 -10 -20 5 -3 3.5 +5 9 0
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz mA mA mA % % dBm k dBc/Hz dBc/Hz dBc/Hz V MHz GHz GHz dB dBm dBm dBm dBm k k V V A A pF W W mW mW mW
1 1 2.0 0.8 12 12 3 2 1.7 65 60 350 2.5 2 100 75 435
Rev. A | Page 4 of 32
AD9858
Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width Low (tPWL) Minimum Clock Pulse Width High (tPWH) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS) Mimimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) Parallel Control Bus WR Minimum Low Time WR Minimum High Time WR Minimum Period Address to WR Setup (TASU) Address to WR Setup (TAHU) Data to WR Setup (TDSU) Data to WR Hold (TDHU) Miscellaneous Timing Specifications REFCLK to SYNCLK FUD to SYNCLK Setup Time FUD to SYNCLK Hold Time REFCLK to SYNCLK Delay FUD Rising Edge to Frequency Change Single Tone Mode Linear Sweep Mode FUD Rising Edge to Phase Offset Change Temp Test Level Min Typ Max Unit
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C 25C
IV IV IV IV IV IV IV IV IV IV IV IV IV IV V IV IV IV IV IV IV
10 5.5 15 1 7 0 20 3 6 9 3 0 3.5 0 2.5 4 0 2.5 3 83 99 83
MHz ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns sysclk cycles sysclk cycles sysclk cycles
1 2
The reference clock input is configured to accept a differential or single-ended sine wave input or a 3 V CMOS-level pulse input. REFCLK input is internally dc biased. AC coupling should be used. 3 Reference clock frequency is selected to ensure second harmonic is out of the bandwidth of interest. 4 PD inputs sent @ 400 MHz, with divide-by-4 enabled. 5 The charge pump current is programmable in eight discrete steps, minimum value assumes current sharing. 6 For 0.75 V < VCP < CPVDD - 0.75 V. 7 These differential inputs are internally dc biased. AC coupling should be used. 8 The charge pump supply voltage can range from 4.75 V to 5.25 V. 9 Output interface is differential open collector. 10 For 1 dB output compression; input power measured at 50 .
Rev. A | Page 5 of 32
AD9858 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter AVDD DVDD CPVDD Digital Input Voltage Digital Output Current Storage Temperature Operating Temperature JA EPAD Soldered Rating 4V 4V 6V -0.7 V to +VDD 5 mA -65C to +150C -40C to +85C 25C/W
Table 3. Explanation of Test Levels
I III IV V VI 100% Production Tested. Sample Tested Only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. Devices are 100% production tested at 25C and guaranteed by design and characterization testing for industrial operating temperature range.
Absolute Maximum Ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 32
AD9858 PIN CONFIGURATION
SPSELECT SYNCLK DACISET RESET DGND DGND DACBP AGND AGND AGND AGND AVDD AVDD DVDD DVDD AVDD FUD PS1 PS0 AVDD
77
IOUT
IOUT
IOUT
IOUT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
76
NC
D7 D6 D5 D4 DGND DGND DVDD DVDD D3
1 2 3 4 5 6 7 8 9
75 74 73 72 71 70 69 68 67 66 65
NC AGND AVDD DIV DIV AVDD AGND CPGND CPVDD CP CP CPFL CPGND CPVDD CPISET NC NC PFD PFD IF IF RF RF AGND AVDD
D2 10 D1 11 D0 12 ADDR5 13 ADDR4 14 ADDR3 15 ADDR2/IORESET 16 ADDR1/SDO 17 ADDR0/SDIO 18 WR/SCLK 19 DVDD DGND
20 21
A D 98 58
T O P V IE W ( N ot t o S c a le )
64 63 62 61 60 59 58 57 56 55 54 53 52 51
RD/CS 22 DVDD 23 DVDD
24
25 DVDD 13
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
LO
REFCLK
REFCLK
DVDD
DVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
LO
AVDD
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AGND
AGND
NC = NO CONNECT
Figure 2. 100-Lead EPAD (SV-100) Pin Configuration
Rev. A | Page 7 of 32
03166-A-044
AD9858 PIN FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions--100-Lead EPAD (SV-100)
Pin No. 1 to 4, 9 to 12 5, 6, 21, 28, 95, 96 7, 8, 20, 23 to 27, 93, 94 13 to 18 Mnemonic D7 to D0 DGND DVDD ADDR5 to ADDR0 IORESET I I/O I Description Parallel Port DATA. Note that the functionality of these pins is valid only when the I/O port is configured as a parallel port. Digitial Ground. Digital Supply Voltage. When the I/O port is configured as a parallel port, these pins serve as a 6-bit address select for accessing the on-chip registers (see the IORESET, SDO, and SDIO pins below for serial port mode). Note that this is valid only for serial programming mode. Active high input signal that resets the serial I/O bus controller. It is intended to serve as a means of recovering from an unresponsive serial bus caused by improper programming protocol. Asserting an I/O reset does not affect the contents of previously programmed registers nor does it invoke their default values. Note that this is valid only for serial programming mode. When operating the I/O port as a 3-wire serial port, this pin serves as a unidirectional serial data output pin. When operated as a 2-wire serial port, this pin is unused. Note that this is valid only for serial programming mode. When operating the I/O port as a 3-wire serial port, this pin is the serial data input. When operated as a 2-wire serial port, this pin is the bidirectional serial data pin. When the I/O port is configured for parallel programming mode, this pin functions as an active low write pulse (WR). When configured for serial programming mode, this pin functions as the serial data clock (SCLK). When the I/O port is configured for parallel programming mode, this pin functions as an active low read pulse (RD). When configured for serial programming mode, this pin functions as an active low chip select (CS) that allows multiple devices to share the serial bus. Analog Ground.
16
I
17
SDO
O
18
SDIO
I or I/O I
19
WR/SCLK
22
RD/CS
I
29, 30, 37 to 39, 41, 42, 49, 50, 52, 69, 74, 80, 85, 87, 88 31, 32, 35, 36, 40, 43, 44, 47, 48, 51, 70, 73, 77, 86, 89, 90 33 34 45 46 53 54 55 56 57 58 59, 60, 75, 76 61 62, 67 63, 68 64 65, 66
AGND
I
AVDD
I
Analog Supply Voltage.
REFCLK REFCLK LO LO RF RF IF IF PFD PFD NC CPISET CPVDD CPGND CPFL CP
I I I I I I O O I I I I I O O
Reference Clock Complementary Input. (Note that when the REFCLK port is operated in singleended mode, REFCLK should be decoupled to AVDD with a 0.1 F capacitor. Reference Clock Input. Mixer Local Oscillator (LO) Complementary Input. Note that when the LO port is operated in single-ended mode, LO should be decoupled to AVDD with a 0.1 F capacitor. Mixer Local Oscillator (LO) Input. Analog Mixer RF Complementary Input. Note that when the RF port is operated in single-ended mode, RF should be decoupled to AVDD with a 0.1 F capacitor. Analog Mixer RF Input. Analog Mixer IF Output. Analog Mixer IF Complementary Output. Phase Frequency Detector Complementary Input . Note that when the PFD port is operated in single-ended mode, PFD should be decoupled to AVDD with a 0.1 F capacitor. Phase Frequency Detector Input. No Connection. Charge Pump Output Current Control. A resistor connected from CPISET to CPGND establishes the reference current for the charge pump. Charge Pump Supply Voltage. Charge Pump Ground. Charge Pump Fast Lock Output. Charge Pump Output.
Rev. A | Page 8 of 32
AD9858
Pin No. 71 72 78 79 81, 82 83, 84 91 92 97, 98 99 100 Mnemonic DIV DIV DACBP DACISET IOUT IOUT SPSELECT RESET PS0, PS1 FUD SYNCLK I/O I I Description Phase Frequency Detector Feedback Input. Phase Frequency Detector Feedback Complementary Input. Note that when the DIV port is operated in single-ended mode, DIV should be decoupled to AVDD with a 0.1 F capacitor. DAC Baseline Decoupling Pin, Typically Bypassed to Pin 77 with a 0.1 F Capacitor. A Resistor Connected from DACISET to AGND Establishes the Reference Current for the DAC. DAC Output. DAC Complementary Output. I/O Port Serial/Parallel Programming Mode Select Pin. Logic 0: serial programming mode. Logic 1: parallel programming mode. Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9858 to its default operating conditions. Used to Select One of the Four Internal Profiles. These pins are synchronous to the SYNCLK output. Frequency Update. The rising edge transfers the contents of the internal buffer registers to the memory registers. This pin is synchronous to the SYNCLK output. Clock Output Pin that Serves as a Synchronizer for External Hardware. SYNCLK runs at REFCLK/8.
I O O I I I I O
Rev. A | Page 9 of 32
AD9858 TYPICAL PERFORMANCE CHARACTERISTICS
0 -10 -20 -30 -40 -50 -60 -70 -80
03166-A-002
REF LVL 5dBm 1
MARKER 1 [T1] 1.04dBm 26.05210421MHz
RBW VBW SWT
5kHz RF ATT 5kHz 50s UNIT
20dB dB REF LVL 5dBm
MARKER 1 [T1] 1.73dBm 26.10050100MHz 1
RBW VBW SWT
200Hz RF ATT 200Hz 64s UNIT
20dB dB A
0
A
-10 -20
1AP
-30 -40 -50 -60 -70 -80 -90 -100 CENTER 26.1MHz 50kHz/ SPAN 500kHz
1AP
-90 -100 START 0Hz 50MHz/ STOP 500MHz
Figure 3. Wideband SFDR, 26 MHz FOUT
REF LVL 5dBm MARKER 1 [T1] 1.72dBm 65.13026052MHz 1 A RBW VBW SWT 5kHz RF ATT 5kHz 50s UNIT 20dB dB
Figure 6. Narrow-Band SFDR, 26 MHz FOUT, 1 MHz BW
REF LVL 5dBm MARKER 1 [T1] 1.58dBm 65.10200401MHz 1 A RBW VBW SWT 500Hz RF ATT 500Hz 40s UNIT 20dB dB
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
0 -10 -20
1AP
-30 -40 -50 -60 -70 -80
1AP
03166-A-003
-90 -100 CENTER 65.1MHz 200kHz/ SPAN 2MHz
START 0Hz
50MHz/
STOP 500MHz
Figure 4. Wideband SFDR, 65 MHz FOUT
REF LVL 5dBm MARKER 1 [T1] 1.39dBm 126.25250501MHz 1 RBW VBW SWT 5kHz RF ATT 5kHz 50s UNIT 20dB dB
Figure 7. Narrow-Band SFDR, 65 MHz FOUT, 1 MHz BW
REF LVL 5dBm MARKER 1 [T1] 1.27dBm 126.10200401MHz 1 A RBW VBW SWT 500Hz RF ATT 500Hz 40s UNIT 20dB dB
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 START 0Hz
0
A
-10 -20
1AP
-30 -40 -50 -60 -70 -80
1AP
03166-A-004
-90 -100 CENTER 126.1MHz 200kHz/ SPAN 2MHz
50MHz/
STOP 500MHz
Figure 5. Wideband SFDR, 126 MHz FOUT
Figure 8. Narrow-Band SFDR, 126 MHz FOUT, 1 MHz BW
Rev. A | Page 10 of 32
03166-A-008
03166-A-007
03166-A-006
AD9858
REF LVL 5dBm MARKER 1 [T1] -1.25dBm 375.75150301MHz RBW VBW SWT 5kHz RF ATT 5kHz 50s UNIT 1 A 20dB dB REF LVL 5dBm MARKER 1 [T1] -1.35dBm 375.10501002MHz 1 A RBW VBW SWT 500Hz RF ATT 500Hz 100s UNIT 20dB dB
0 -10 -20 -30 -40 -50 -60 -70 -80
0 -10 -20
1AP
-30 -40 -50 -60 -70 -80
1AP
03166-A-005
-90 -100 START 0Hz 50MHz/ STOP 500MHz
-90 -100 CENTER 375.1MHz 500kHz/ SPAN 5MHz
Figure 9. Wideband SFDR, 375 MHz FOUT
REF LVL 5dBm RBW VBW SWT 300Hz RF ATT 300Hz 56s UNIT 20dB dB
Figure 12. Narrow-Band SFDR, 375 MHz FOUT, 1 MHz BW
REF LVL 5dBm MARKER 1 [T1] 1.12dBm 216.43286573MHz 1 RBW VBW SWT 5kHz 5kHz 50s RF ATT UNIT 20dB dB A
0
A
0 -10 -20
1AP
-10 -20 -30 -40 -50 -60 -70 -80
03166-A-010
-30 -40 -50 -60 -70 -80 -90 -100 START 0Hz 50MHz/ STOP 500MHz
1AP
-90 -100 CENTER 216.1MHz 100kHz/ SPAN 1MHz
Figure 10. Narrow-Band SFDR, 201 MHz FOUT, 1 MHz BW, 1 GHz Clock, Divider Off
REF LVL 5dBm RBW VBW SWT 300Hz RF ATT 300Hz 56s UNIT 20dB dB
Figure 13. Wideband SFDR, 201 MHz FOUT, 1GHz Clock, Divider Off
MARKER 1 [T1] 1.12dBm 216.43286573MHz 1 RBW VBW SWT 5kHz 5kHz 50s RF ATT UNIT 20dB dB A
REF LVL 5dBm
0
A
0 -10 -20
1AP
-10 -20 -30 -40 -50 -60 -70 -80
03166-A-012
-30 -40 -50 -60 -70 -80 -90 -100 START 0Hz 50MHz/ STOP 500MHz
1AP
-90 -100 CENTER 216.1MHz 100kHz/ SPAN 1MHz
Figure 11. Narrow-Band SFDR, 201 MHz FOUT, 1 MHz BW, 2 GHz Clock, Divider On
Figure 14. Wideband SFDR, 201 MHz FOUT, 2 GHz Clock, Divider On
Rev. A | Page 11 of 32
03166-A-013
03166-A-011
03166-A-009
AD9858
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1K 10K 100K FREQUENCY (Hz) 1M 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1K 10K 100K FREQUENCY (Hz) 1M
PHASE NOISE, L(f) (dBc/Hz)
03166-A-014
PHASE NOISE, L(f) (dBc/Hz)
10M
10M
Figure 15. Residual Phase Noise, 103 MHz FOUT, 1 GHz REFCLK
Figure 18. Residual Phase Noise, 403 MHz FOUT, 1 GHz REFCLK
PHASE NOISE, L(f) (dBc/Hz)
-50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M
PHASE NOISE, L(f) (dBc/Hz)
0 -10 -20 -30 -40
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 100 1K 10K 100K FREQUENCY (Hz) 1M 10M
03166-A-016
100M
100M
Figure 16. Fractional Divider Loop Residual Phase Noise, FIN = 115 MHz, FOUT = 1550 MHz, Loop BW = 50 kHz
DELTA 1 [T1] REF LVL 0dBm 0.0dB 0.00000000Hz RBW VBW SWT 1kHz 1kHz 3.8s RF ATT UNIT 10dB dBm
Figure 19. Translation Loop Residual Phase Noise FLO = 1500 MHz, FOUT = 1550 MHz, Loop BW = 50 kHz
REF LVL 0dBm DELTA 1 [T1] -56.76dB 423.84769539kHz 1 A RBW VBW SWT 2kHz 2kHz 940s RF ATT UNIT 10dB dBm
0
A
0 -10 -20
1AP
-10 -20 -30 -40 -50 -60 -70 -80 -90
1
03166-A-018
-30 -40 -50 -60 -70 -80 -90 -100 CENTER 1.55GHz 150kHz/ SPAN 1.5MHz
1
1AP
-100 CENTER 1.55GHz 150kHz/ SPAN 1.55MHz
Figure 17. Fractional Divider Loop SFDR, FIN = 96.9 MHz, FOUT = 1550 MHz, BW = 1.5 MHz
Figure 20. Fractional Divider Loop SFDR, FIN = 97.3 MHz, FOUT = 1550 MHz, BW = 1.5 MHz
Rev. A | Page 12 of 32
03166-A-021
03166-A-019
03166-A-015
AD9858
DELTA 1 [T1] REF LVL 0dBm 0.0dB 0.00000000Hz RBW VBW SWT 5kHz 5kHz 15s RF ATT UNIT 10dB dBm A REF LVL 0dBm DELTA 1 [T1] -64.55dB -1.20240481MHz 1 RBW VBW SWT 5kHz 5kHz 15s RF ATT UNIT 10dB dBm A
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 CENTER 1.55GHz 15MHz/ SPAN 150MHz
1
0 -10 -20
1AP
-30 -40 -50 -60 -70 -80
1
1AP
03166-A-017
-90 -100 CENTER 1.55GHz 15MHz/ SPAN 150MHz
Figure 21. Fractional Divider Loop SFDR, FIN = 96.9 MHz, FOUT = 1550 MHz, BW = 150 MHz
REF LVL 0dBm DELTA 1 [T1] -81.10dB 57.11422845kHz RBW VBW SWT 1kHz 500kHz 7.6s RF ATT UNIT 10dB dBm
Figure 24. Fractional Divider Loop SFDR, FIN = 97.3 MHz, FOUT = 1550 MHz, BW = 150 MHz
REF LVL 0dBm DELTA 1 [T1] -60.67dB -57.11422846kHz 1 A RBW VBW SWT 1kHz RF ATT 500Hz 7.6s UNIT 10dB dBm
0 -10 -20 -30 -40 -50 -60 -70 -80
1
0
A
-10 -20
1AP
-30 -40 -50 -60 -70 -80
1
1AP
03166-A-022
-90 -100 CENTER 1.55GHz 150kHz/ SPAN 1.5MHz
-90 -100 CENTER 1.55GHz 150kHz/ SPAN 1.5MHz
Figure 22. Translation Loop SFDR, FLO = 1459 MHz, FOUT = 1550 MHz, BW = 1.5 MHz
REF LVL 0dBm DELTA 1 [T1] -96.36dB -42.98597194MHz 1 RBW VBW SWT 10kHz RF ATT 500Hz 75s UNIT 10dB dBm A
Figure 25. Translation Loop SFDR, FLO = 1410 MHz, FOUT = 1550 MHz, BW = 1.5 MHz
REF LVL 0dBm DELTA 1 [T1] -64.55dB -1.20240481MHz 1 A RBW VBW SWT 5kHz 5kHz 15s RF ATT UNIT 10dB dBm
0 -10 -20 -30 -40 -50 -60 -70 -80
0 -10 -20
1AP
-30 -40 -50 -60 -70 -80
1
1AP
03166-A-023
-90 -100
1
-90 -100 CENTER 1.55GHz 15MHz/ SPAN 150MHz
CENTER 1.55GHz
15MHz/
SPAN 150MHz
Figure 23. Translation Loop SFDR, FLO = 1459 MHz, FOUT = 1550 MHz, BW = 150 MHz
Figure 26. Translation Loop SFDR, FLO = 1410 MHz, FOUT = 1550 MHz, BW = 150 MHz
Rev. A | Page 13 of 32
03166-A-046
03166-A-045
03166-A-020
AD9858
2.0 1.8 1.6
600 3.3V 500 3.5V
POWER DRAWN (W)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 225 450 675 REF CLOCK (MHz) 900
03166-A-025
SUPPLY CURRENT (mA)
400
3.1V
300
200
1125
0
0
70
140
210 FOUT (MHz)
280
350
420
Figure 27. Supply Current vs. REFCLK (FOUT = REFCLK/5)
Figure 28. Supply Current vs. FOUT (1 GHz REFCLK)
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03166-A-024
100
AD9858 THEORY OF OPERATION
OVERVIEW
The AD9858 direct digital synthesizer (DDS) is a flexible device that can address a wide range of applications. The device consists of an NCO with a 32-bit phase accumulator, 14-bit phase offset adjustment, a power efficient DDS core, and a one giga-samples per second (1 GSPS) 10-bit digital-to-analog converter. The AD9858 incorporates additional capabilities for automated frequency sweeping. The device also offers an analog mixer capable of operating at 2 GHz, a phase-frequency detector (PFD), and a programmable charge pump (CP) with advanced fast-lock capability. These RF building blocks can be used for various frequency synthesis loops or as needed in system design. The AD9858 can directly generate frequencies up to 400+ MHz when driven at a 1 GHz internal clock speed. This clock can be derived from an external clock source of up to 2 GHz by using the on-chip divide-by-2 feature. The on-chip mixer and PFD/CP make possible a variety of synthesizer configurations capable of generating frequencies in the 1 GHz to 2 GHz range or higher. The AD9858 offers the advantages of a DDS with the additional flexibility to work in concert with analog frequency synthesis techniques (PLL, mixing) to generate precision frequency signals with high frequency resolution, fast frequency hopping, fast settling time, and automated frequency sweeping capabilities. Writing data to its on-chip digital registers that control all operations of the device easily configures the AD9858. The AD9858 offers a choice of both serial and parallel ports for controlling the device. Four user profiles can be selected by a pair of external pins. These profiles allow independent setting of the frequency tuning word and the phase offset adjustment word for each of four selectable configurations. The AD9858 can be programmed to operate in single-tone mode or in frequency-sweeping mode. To save on power consumption, there is also a programmable full-sleep mode, during which most of the device is powered down to reduce current flow. The operation of a DDS is described in detail in a tutorial available from Analog Devices at www.analog.com/dds. programmed frequency tuning word (FTW). The relation of the output frequency of the device to the system clock (SYSCLK) is determined by the following equation:
FO =
(FTW x SYSCLK )
2N
where for the AD9858, N = 32. For a more detailed explanation of a DDS core, consult the DDS tutorial at www.analog.com/dds.
DAC Output
The AD9858 incorporates an integrated 10-bit current output DAC. Two complementary outputs provide a combined fullscale output current (IOUT). Differential outputs reduce the amount of common-mode noise that might be present at the DAC output, offering the advantage of an increased signal-tonoise ratio. The full-scale current is controlled by means of an external resistor (RSET) connected between the DACISET pin and analog ground. The full-scale current is proportional to the resistor value as follows:
RSET = 39.19 / I OUT
The maximum full-scale output current of the combined DAC outputs is 40 mA, but limiting the output to 20 mA provides the best spurious-free dynamic range (SFDR) performance. The DAC output compliance range is (AVDD - 1.5 V) to (AVDD + 0.5 V). Voltages developed beyond this range cause excessive DAC distortion and could potentially damage the DAC output circuitry. Proper attention should be paid to the load termination to keep the output voltage within this compliance range. When terminating the differential outputs into a transformer, the center tap should be attached to AVDD.
PLL Frequency Synthesizer
The PLL frequency synthesizer is a group of independent synthesis blocks, designed to be used with the DDS to expand the range of synthesis applications. These blocks are a digital phase-frequency detector (PFD) that drives a charge pump (CP). The charge pump incorporates fast-locking logic, described below. Based on system requirements, the user supplies an external loop filter and one or more VCOs. A high speed analog mixer is included for translation synthesis loops. Using the different blocks in the PLL frequency synthesizer in conjunction with the DDS, the user can create translation loops (also known as offset loops), fractional divider loops, as well as traditional PLL loops to multiply the output of the DDS in frequency.
COMPONENT BLOCKS
DDS Core
The DDS core generates the numeric values that represent a sinusoid in the digital domain. Depending on the operating mode of the DDS, this sinusoid may be changed in frequency, phase, or perhaps modulated by an information carrying signal. The frequency of the output signal is determined by a user-
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AD9858
Phase-Frequency Detector
The phase detector has two inputs, PDIN and DIVIN. Both are analog inputs that can be operated in differential or singleended mode. Both are designed to operate at frequencies up to 150 MHz, although signals of up to 400 MHz can be accommodated on the inputs when the divide-by-4 functions are used. The expected input level for both the PD and DIV inputs is in the range of 800 mV p-p (differential), 400 mV p-p (single-ended). A programmable divider that offers division ratios of M, N = {1, 2, 4} immediately follows the input. The division ratio is controlled by means of the control function register. combination of programmable output current, programmable polarity, wide compliance range, and proprietary fast-lock capability offers the flexibility necessary for the digital PLL to operate within a broad range of PLL applications.
Fast-Locking Logic
The charge pump includes a fast-locking algorithm that helps to overcome the traditional limitations of PLLs with regard to frequency switching time. The fast-locking algorithm works in conjunction with the loop filter shown in Figure 29 to provide extremely fast frequency switching performance. Based on the error seen between the feedback signal and the reference signal, the fast-locking algorithm puts the charge pump into one of three states: frequency detect mode, a wide closed-loop mode, and a final closed-loop mode. In the frequency detect mode, the feedback and reference signals are registering substantial phase and frequency errors. Rather than operating in a continuous closed-loop feedback mode, the charge pump supplies a fixed current of the correct polarity to the VCO control node that drives the loop towards frequency lock. Once frequency lock is detected, the fast-locking logic shifts the part into one of the closed-loop modes. In the closedloop modes, either wide or final, the charge pump supplies current to the loop filter as directed by the phase-frequency detector PFD. The frequency-detect mode is intended to bring the system to a level of frequency lock from which the intermediary closed-loop system can quickly achieve phase lock. The level of frequency lock accuracy aimed for is typically referred to as the lock range. Once the frequency is within the lock range, the time required to achieve phase lock can be determined by standard PLL transient analysis methods. Note that the charge pump current sources associated with the frequency detect mode are connected to Pin 64, while the closed loop current sources are connected to Pins 65 and 66. Pin 64 is connected directly to the loop filter zero compensation capacitor, as shown in Figure 29. This connection allows the smoothest transition from the frequency detect mode to the closed-loop modes and enables faster overall switching times. Pins 65 and 66 are connected to the loop filter in the conventional manner.
CP R2
03166-A-032
Charge Pump
The charge pump output reference current is determined by an external resistor (~2.4 k), which establishes a 500 A maximum internal baseline current (ICP0). The baseline current is scaled to provide the appropriate drive current for the CP's various operating modes (frequency detect mode, wide closedloop, and final closed-loop). The amount of scaling in each mode is programmable by means of the values stored in the control function register, giving the user maximum flexibility of the PLL's frequency locking capability. The CP polarity can be configured as either positive or negative with respect to the PD input. When the CP polarity is positive, if the DIV input leads the PD input, the charge pump attempts to decrease the voltage at the VCO control node. If the DIV input lags the PD input, the charge pump works to increase the voltage at the VCO control node. When the CP polarity is negative, the opposite occurs. This allows the user to define either input as the feedback path. This also allows the AD9858 to accommodate ground-referenced or supply-referenced VCOs. This functionality is defined by the charge pump polarity (CPP) bit in the control function register. When CPP = 0 (default), the charge pump is set up for operation with a ground-referenced VCO. When CPP = 1, the charge pump is set up for a supply-referenced VCO. Internal to the CP, the ICP0 current is scaled to provide different output drive current values for the various modes of operation. In its normal operating mode, the final closed-loop mode can be programmed to scale ICP0 by 1, 2, 3, or 4. Setting the charge pump current offset bit, CFR<13>, applies a 2 mA offset to the programmed charge pump current, allowing scaler values of ICP0 of 5, 6, 7, or 8. The wide closed-loop mode can be programmed to scale ICP0 by 0, 2, 4, 6, 8, 10, 12, or 14. The frequency detect mode can be programmed to scale ICP0 by 0, 20, 40, or 60. The different modes of operation, controlled by the fast-locking logic, are discussed in the next section The CP has an independent set of power pins that can operate at up to 5.25 V. While the device can operate from ground to rail, the voltage compliance should be kept in the range of 0.5 V to 4.5 V to ensure the best steady-state performance. The
AD9858
CP CPFL
C2
Figure 29. Symbolic Representation of Charge Pump to Loop Filter Connection
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AD9858
The frequency detection block works as follows. The comparison logic in the frequency detection circuitry operates one eighth of the DDS system clock. A comparison is made of the frequencies present at the PD input and the DIV input over 19 DDS clock cycles. To ensure that frequency lock detection is achieved while the frequency difference is within the PLL lock range, the slew rate of the VCO input should be limited such that the lock range cannot be traversed within 152 system clock cycles. The slew rate of the VCO input is determined by the programmed level of frequency detect current and the size of the zero compensation capacitor according to the following relationship:
dv dt = If
det
TIME
shifts the charge pump into intermediary closed-loop mode, resulting in a shorter overall frequency switching time.
VCO VOLTAGE
CZ
Once frequency detection occurs, the loop is closed and the loop is lock based on the current programmed for the wide closed-loop mode. It is important that the loop be designed for closed-loop stability while in the wide closed-loop mode. In this mode, less phase margin can usually be tolerated, because this mode is only used to enhance the lock time, but is not used in the "locked" free running state. Once the wide closed-loop mode achieves phase lock as determined by an internal lock detector, the phase-detector/charge pump transitions into the final closed-loop state. If no wide closed-loop current is programmed, the loop transitions directly from the frequency detect mode into the final closed-loop state. In the final closedloop state, the loop characteristics should be optimized for the desired free running loop bandwidth. The frequency detect mode is primarily useful in offset or translation loop applications where the phase detector inputs are more likely to detect large frequency transitions. For loop applications with significant amounts of division in the feedback loop, the frequency detection mode may not activate. This is due to the limited amount of frequency difference that is experienced at the phase detector inputs. For these applications, the primary means of accelerating the frequency settling time is to design the loop to acquire lock with the wide closed-loop setting and then switch to the final closed-loop setting. As mentioned earlier, care should be taken when planning for a large transition using the frequency detect mode to ensure that the charge pump does not cause the VCO to overshoot the closed-loop lock range, as cycle slipping could occur, which would result in extended delays. Figure 30 shows two system responses. In the first, the charge pump output current is maximized during the frequency-detect mode so that, after 152 clock cycles, the VCO voltage has exceeded the closed-loop lock range. The second system provides less current during the frequency detect mode. While this results in a longer delay in approaching the closed-loop lock range, because the system does not exceed the closed-loop range, the fast-locking logic
Figure 30. Symbolic Representation of Charge Pump to Loop Filter Connection
Analog Mixer
The analog mixer is included for translation loops, also known as offset loops. The radio frequency (RF) and local oscillator (LO) inputs are designed to operate at frequencies up to 2 GHz. Both inputs are differential analog input stages. Both input stages are internally dc biased and should be connected through an external ac coupling mechanism. The expected input level is in the range of 800 mV p-p (differential). The IF (intermediate frequency) output is a differential analog output stage designed to operate at frequencies less than 400 MHz. This mixer is based on the Gilbert cell architecture.
MODES OF OPERATION
The AD9858 DDS section has three modes of operation--single tone, frequency sweeping, and full sleep. The RF building blocks (PFD, CP, and mixer) can be active or powered down, used or unused, in either of the active modes. In the single-tone mode, the device generates a single output frequency determined by a 32-bit word (frequency tuning word--FTW) loaded to an internal register. This frequency can be changed as desired, and frequency hopping can be accomplished at a rate limited only by the time required to update the appropriate registers. If even faster hopping is needed, the four profiles allow rapid hopping among the four frequencies stored in them by means of external select pins. The frequency-sweeping mode allows for the automation of most of the frequency-sweeping task, making chirp and other frequency-sweeping applications possible without the inconvenience and possible speed limitations imposed by multiple register operations via the I/O port. In whichever mode the device is operating, changes in frequency are phase continuous, which means that they do not cause discontinuities in the phase of the output signal. The first phase value after a frequency change is an increment of the last
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AD9858
phase value before the change, but at the new tuning word's phase increment value (FTW). (Note that this is not the same as phase-coherent over frequency changes; see Figure 31.)
REFERENCE SIGNAL
FREF = A
FREF = A
FREF = A
The maximum usable frequency in the fundamental range of the DDS is typically between 40% and 45% of the Nyquist frequency, depending on the reconstruction filter. With a 1 GHz SYSCLK, the AD9858 is capable of producing maximum output frequencies of between 400 MHz and 450 MHz, depending on the reconstruction filter and the application system requirements. For a desired output frequency (FO) and sampling rate (SYSCLK), the frequency tuning word (FTW) of the AD9858 is calculated according to the following equation
FTW = FO x 2 N / SYSCLK
PHASE CONTINUOUS FOUT = A
= REF
FOUT = 2A
= 2REF
FOUT = 2A
= 2REF+ + '
PHASE COHERENT FOUT = A
= REF
FOUT = 2A
= 2REF
(
)
FOUT = A
= REF
where N is the phase accumulator resolution in bits (32 in the AD9858), FO is in Hz, and the FTW is a decimal number.
03166-A-034
WHERE = PHASE OF OUTPUT SIGNAL, = PHASE AT TIME OF FIRST FREQUENCY TRANSITION, AND ' = PHASE AT TIME OF SECOND FREQUENCY TRANSITION.
Figure 31. The Difference between a Phase Continuous Frequency Change and a Phase Coherent Frequency Change
Once a decimal number has been calculated, it must be rounded to an integer and converted to a 32-bit binary value. The frequency resolution of the AD9858 is 0.233 Hz when the SYSCLK is 1 GHz.
Single-Tone Mode
When in single-tone mode, the AD9858 generates a signal, or tone, of a single desired frequency. This frequency is set by the value loaded by the user into the chip's frequency tuning word (FTW) register. This frequency can be between 0 Hz and somewhat below one-half of the DAC sampling frequency (SYSCLK). One-half of the sampling frequency is commonly called the Nyquist frequency. The practical upper limit to the fundamental frequency range of a DDS is determined by the characteristics of the external low-pass filter, known as the reconstruction filter, which must follow the DAC output of the DDS. This filter reconstructs the desired analog sine wave output signal from the stream of sampled amplitude values output by the DAC at the sample rate (SYSCLK). A DDS is a sampled-data system. As the fundamental frequency of the DDS approaches the Nyquist frequency, the lower first image approaches the Nyquist frequency from above. As the fundamental frequency approaches the Nyquist frequency, it becomes difficult, and finally impossible, to design and construct a low-pass filter that will provide adequate attenuation for the first image frequency component.
Frequency-Sweeping Mode
The AD9858 provides automated frequency sweeping capability. This allows the AD9858 to generate frequency-swept signals for chirped radar or other applications. The AD9858 includes features that automate much of the task of executing frequency sweeps. The frequency sweep feature is implemented through the use of a frequency accumulator (not to be confused with the phase accumulator). The frequency accumulator repeatedly adds a frequency incremental quantity to the current value, thereby creating new instantaneous frequency tuning words, causing the frequency generated by the DDS to change with time. The frequency increment, or step size, is loaded into a register known as the delta frequency tuning word (DFTW). The rate at which the frequency is incremented is set by another register, the delta frequency ramp rate word (DFRRW). Together these two registers enable the AD9858 to sweep from a beginning frequency set by the FTW, upwards or downwards, at a desired rate and frequency step size. The result is a linear frequency sweep or chirp.
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AD9858
FREQUENCY
DELTA FREQUENCY RAMP RATE WORD ( 8ns) TIME TIME
Figure 32. Frequency vs. Time Plots for a Given Sweep Profile
The delta frequency ramp rate word (DFRRW) functions as a countdown timer, in which the value of the DFRRW is decremented at the rate of SYSCLK/8. This means that the most rapid frequency word update occurs when a value of 1 is loaded into the DFRRW, and results in a frequency increment at 1/8 of the SYSCLK rate. With a SYSCLK of 1 GHz, the frequency can be incremented at a maximum rate of 125 MHz (DFRRW = 1). The delta frequency tuning word (DFTW) must specify whether the frequency sweep should proceed up or down from the starting frequency (FTW). Therefore, the DFTW is expressed as a twos complement binary value, in which positive indicates up and negative indicates down. A DFRRW value of 0 written to the register stops all frequency sweeping. There is no automatic stop-at-a-given-frequency function. The user must calculate the time interval required to reach the final frequency and then issue a command to write 0 into the DFRRW register. The time required for a frequency sweep is calculated by the following formula
The time between each frequency step (t) is given by
t =
8 x DFRRW SYSCLK
The value of the stop frequency fF is determined by
fF = fS + T x f t
Returning to Starting Frequency
The original frequency tuning word (FTW), which was written into the frequency tuning register, does not change at any time during a sweeping operation. This means that the DDS may be returned to the sweep starting frequency at any time during a sweep. Setting the control bit named autoclear frequency accumulator forces the frequency accumulator to zero, instantly returning the DDS to the frequency stored as FTW.
Full-Sleep Mode
Setting all of the power-down bits in the control function register activates full-sleep mode. During the power-down condition, the clocks associated with the various functional blocks of the device are turned off, thereby offering a significant power savings.
T= where:
f F - f S x 2 34 SYSCLK 2
DFRRW x DFTW
T is the duration of the sweep in seconds. fS is the starting frequency determined by
fS = FTW x SYSCLK . 2 32
SYNCHRONIZATION
SYNCLK and FUD Pins
Timing for the AD9858 is provided via the user-supplied REFCLK input. The REFCLK input is buffered and is the source for the internally generated SYSCLK. The frequency of SYSCLK can be either the same as REFCLK or half that of REFCLK (via a programmable divide-by-2 function set in the control function register CFR). The REFCLK input is capable of handling input frequencies as high as 2 GHz. However, the device is designed for a maximum SYSCLK frequency of 1 GHz. Thus, it is mandatory that the divide-by-2 SYSCLK function be enabled when the frequency of REFCLK is greater than 1 GHz.
fF is the final frequency. The delta frequency step size is given by
f =
DFTW x SYSCLK , 2 31
remembering that DFTW is a signed (twos complement) value.
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8ns
16ns
24ns
32ns
FREQUENCY
DELTA FREQUENCY TUNING WORD
40ns
80ns
120ns
160ns
AD9858
SYSCLK serves as the sample clock for the DAC and is fed to a divide-by-8 frequency divider to produce SYNCLK. SYNCLK is provided to the user on the SYNCLK pin. This enables synchronization of external hardware with the AD9858's internal DDS clock. External hardware that is synchronized to the SYNCLK signal can then be used to provide the frequency update (FUD) signal to the AD9858. The FUD signal and SYNCLK are used to transfer the internal buffer register contents into the memory registers of the device. Figure 33 shows a block diagram of the synchronization methodology, and Figure 34 shows an I/O synchronization timing diagram. Note that SYNCLK is also used to synchronize the assertion of the profile select pins (PS0, PS1). The FUD, PS0, and PS1 pins must be set up and held around the rising edge of SYNCLK. These device inputs are designed for zero hold time and 3.5 ns setup time.
2 GHz DIVIDER DISABLE
SYNCLK DISABLE
0 /8 SYNCLK
1
SYNCLK
1
REFCLK /2
0
EDGE DETECTION LOGIC
0
D Q P0, P1 D Q FUD
UPDATE REGS
TO CORE LOGIC
REGISTER MEMORY
BUFFER MEMORY
WR ADDR DATA
Figure 33. I/O Synchronization Block Diagram
SYSCLK FUD REGISTERED SYNCLK FUD EDGE DETECTED FUD REGISTERED FUD EDGE DETECTED
FUD*
IO BUFFER MEMORY CONTROL REGISTER DATA
VALUE 1 (ASYNCHRONOUSLY LOADED VIA I/O PORT)
VALUE 2
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
VALUE 0
03166-A-036
VALUE 1
VALUE 2
*FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES OF SYNCLK. THE OCCURRENCE OF
THE RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATEREGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE TRANSFERRED INTO THE CONTROL REGISTERS. SIMILARLY, A STATE CHANGE ON THE PS0 OR PS1 PINS IS EQUIVALENT TO ASSERTING A VALID FUD SEQUENCE. NOTE: I/O UPDATES ARE SYNCHRONOUS TO THE SYNCLK SIGNAL, REGARDLESS OF THE SYNCHRONIZATION MODE SELECTED.
Figure 34. I/O Synchronization Timing Diagram
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AD9858
Frequency Planning
To achieve the best possible spurious performance when using the AD9858 in a hybrid synthesizer configuration, frequency planning can be employed. Frequency planning consists of being aware of the mechanisms that determine the location of the worst-case spurs and then using the appropriate loop tuning parameters to place these spurs either outside the loop bandwidth, such that they are attenuated, or completely outside the frequency range of interest. When using the fractional divider configuration, the worst-case spurs occur whenever the images of the DAC harmonics fold back such that they are close to the DAC fundamental or carrier frequency. If these images fall within the loop bandwidth, they will be gained up by approximately 20 x log N, where N is the gain in the loop. If N is relatively high, these spurs can still realize significant gain even if they are slightly outside the loop bandwidth, since the loop attenuation rate is typically 20 dB/decade in this region. DAC images occur at N x FCLOCK M x FOUT where N and M are integer multiples of FCLOCK and FOUT, respectively. Figure 20 shows a high spurious condition where the low-order odd harmonics are folding back around the fundamental. Figure 21 shows that the worst spurs are confined to a narrow region around the carrier and that wideband spurs are attenuated. Figure 17 shows an alternate frequency plan that results in the same carrier frequency. Recall that the output frequency of the DAC is set by the equation (FOUT = FCLOCK x FTW/2N) This makes it possible to produce the same FOUT by different combinations of FCLOCK and FTW. In this case, the worst DAC spurs are placed well outside the loop bandwidth such that they are attenuated below the noise floor. Figure 24 shows a wideband plot for this frequency plan. Other frequency combinations that can result in high spurious signals are when subharmonics of FCLOCK fall within or near the loop bandwidth. To avoid this, ensure that the DAC FOUT is sufficiently offset from the subharmonics of FCLOCK such that these products are attenuated by the loop. Frequency planning for the translation loop is similar in that the DAC images and the FCLOCK subharmonics need to be considered. Figure 25 and Figure 26 show results for a high spurious configuration where odd order images are folding back close to the carrier. Figure 22 and Figure 23 show an alternative frequency plan that generates the same carrier frequency with low spurious content. Because this loop also requires a mixer LO frequency, additional care is required in planning for this frequency arrangement. Generally there is some mixer LO feedthrough. The amount of feedthrough depends on the PCB board layout isolation as well as the mixer LO power level, but levels of -80 dBc can typically be achieved. Figure 26 shows results for a situation where the mixer LO component shows up in the spectrum at 1.41 GHz, and another spur component shows up at Mixer LO + FCLOCK/8. This places the mixer LO frequency well outside the bandwidth of interest, resulting in the spectrum shown in Figure 25.
PROGRAMMING THE AD9858
The transfer of data from the user to the DDS core of the device is a 2-step process. In a write operation, the user first writes the data to the I/O buffer using either the parallel port (which includes bits for address and data) or serial mode (where the address and data are combined in a serial word). Regardless of the method used to enter data to the I/O buffer, the DDS core cannot access the data until the data is latched into the memory registers from the I/O buffer. Toggling the FUD pin or changing one of the profile select pins causes an update of all elements of the I/O buffer memory into the DDS core's register memory.
I/O Port Functionality
The I/O port can be operated in either serial or parallel programming mode. Mode selection is accomplished via the S/P Select pin. Logic 0 on this pin configures the I/O port for serial programming, while Logic 1 configures the I/O port for parallel programming. The ability to read back the contents of a register is provided in both modes to facilitate the debug process during the user's prototyping phase of a design. In either mode, however, the reading back of profile registers requires that the profile select pins (P0, P1) be configured to select the desired register bank. When reading a register that resides in one of the profiles, the register address acts as an offset to select one of the registers among the group of registers defined by the profile. The profile select pins control the base address of the register bank and select the appropriate register grouping.
Parallel Programming Mode
In parallel programming mode, the I/O port makes use of eight bidirectional data pins (D7 to D0), six address input pins (ADDR5 to ADDR0), a read input pin (RD), and a write input pin (WR). A register is selected by providing the proper address combination as defined in the register map. Read or write functionality is invoked by pulsing the appropriate pin (RD or WR); the two operations are mutually exclusive. The read or write data is transported on the D7 to D0 pins. The correlation between the D7 to D0 data bits and their functionality at a specific register address is detailed in the register map and register bit description. Parallel I/O operation allows write access to each byte of any register in the I/O buffer memory in a single I/O operation at a 100 MHz rate. However, unlike write operation, readback capability is not guaranteed at the 100 MHz rate. It is intended as a low speed function for debug purposes. Timing for both write and read cycles is depicted in Figure 35 and Figure 36.
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AD9858
A<5:0>
A1 A2 A3
D<7:0>
D1
D2
D3
WR
TASU TWRHIGH
TDOU
TWRLOW
TAHD TDHD
TWR
SPECIFICATION
VALUE 3ns 3.5ns 0ns 0ns 3ns 6ns 9ns
DESCRIPTION ADDRESS SETUP TIME TO WR SIGNAL ACTIVE DATA SETUP TIME TO WR SIGNAL INACTIVE ADDRESS HOLD TIME TO WR SIGNAL INACTIVE DATA HOLD TIME TO WR SIGNAL INACTIVE WR SIGNAL MINIMUM LOW TIME WR SIGNAL MINIMUM HIGH TIME WR SIGNAL MINIMUM PERIOD
TASU TDOU TADH TDHD TWRLOW TWRHIGH TWR
Figure 35. I/O Port Write Cycle Timing (Parallel)
A<5:0>
A1
A2
A3
D<7:0>
D1
D2
D3
RD
TRDHOZ TAHD
SPECIFICATION
TRDLOV TADV
VALUE 15ns 5ns 15ns 10ns DESCRIPTION ADDRESS TO DATA VALID TIME (MAXIMUM) ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM) RD LOW TO OUTPUT VALID (MAXIMUM) RD HIGH TO DATA THREE-STATE (MAXIMUM)
03166-A-039
TASU TADH TRDLOV TRDHOZ
Figure 36. I/O Port Read Cycle Timing (Parallel)
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AD9858
Serial Programming Mode
In serial programming mode, the I/O port uses a chip select pin (CS), a serial clock pin (SCLK), an I/O reset pin (IORESET), and either 1 or 2 serial data pins (SDIO and/or SDO). The number of serial data pins used depends on the configuration of the I/O port; i.e., whether it has been configured for 2-wire or 3-wire serial operation as defined by the control function register. In 2-wire mode, the SDIO pin operates as a bidirectional serial data pin. In 3-wire mode, the SDIO pin operates only as a serial data input pin, and the SDO pin acts as the serial output. The maximum rate of SCLK is 10 MHz; however, during read operation, the 10 MHz rate is not guaranteed. The serial port is an SPI compatible serial interface and its operation is virtually identical to that of the AD9852/AD9854. Serial port communication occurs in two phases. Phase 1 is an instruction cycle consisting of an 8-bit word. The MSB of the instruction byte flags the ensuing operation as a read or write operation. The 6 LSBs define the serial address of the target register as defined in the register map. The instruction byte format is given in Table 5.
Table 5.
D7 (MSB) 1: Read 0: Write D6 X D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 DO (LSB) A0
falling edge of SCLK. The bit order for both phases of a serial port communication is selectable via the control function register. The CS pin serves as a chip select control line. When CS is at a Logic 1 state, the SDO and SDIO pins are disabled (forced into a high impedance state). Only when the CS pin is at a Logic 0 state are the SDO and SDIO pins active. This allows multiple devices to exist on a single serial bus. If multiple devices are connected to the same serial bus, then communication with a single device is accomplished by setting CS to a Logic 0 state on the target device, but to a Logic 1 state on all other devices. In this way, serial communication occurs only between the controller and the target device. In the case where I/O synchronization is lost between the AD9858 and the external controller, the IORESET pin provides a means to re-establish synchronization without initializing the entire device. Asserting the active high IORESET pin resets the serial port state machine. This terminates the current I/O operation and puts the device into a state in which the next eight SCLK pulses are expected to be the instruction byte of the next I/O transfer. Note that any information previously written to the memory registers during the last valid communication cycle prior to loss of synchronization remains intact.
Register Map
The registers are listed in Table 6. The serial address and parallel address numbers associated with each of the registers are shown in hexadecimal format. Angle brackets <> are used to reference specific bits or ranges of bits. For example, <3> designates Bit 3, while <7:3> designates the range of bits from 7 down to 3, inclusive.
Phase 2 of a serial port communication contains the data to be routed to/from the addressed register. The number of bytes transferred during Phase 2 depends on the length of the target register. Serial operation requires that all bits associated with a serial register address be transferred. Both phases of a serial port communication require the serial data clock (SCLK) to be operating. When writing to the device, serial bits are transferred on the rising edge of SCLK. When reading from the device, serial output bits are transferred on the
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AD9858
Table 6. Register Map
Register Name Address Ser Par 0x00 <7:0> 0x01 Control Function Register (CFR) <15:8> 0x00 0x02 <23:16> Frequency Detect Charge Pump Current (see Table 7) (MSB) Bit 7 Not Used Freq. Sweep Enable AutoClr Freq. Accum Bit 6 2 GHz Divider Disable Enable Sine Output AutoClr Phase Accum Bit 5 SYNCLK Out Disable Charge Pump Offset Bit Load DeltaFreq Timer Bit 4 Mixer Power Down Bit 3 Phase Detect PwrDwn Bit 2 Power Down (LSB) Bit 1 Bit 0 LSB SDIO First Input Only Charge Phase Detector Pump Divider Ratio Polarity (M) (see Table 11) Don't Use FastFTW Open Lock for Enable FastLock Wide Closed-Loop Charge Pump Current (see Table 9) Default Value 0x18 Profile N/A
Phase Detector Divider Ratio (N) (see Table 10) Clear Freq Accum Clear Phase Accum
0x00
N/A
0x00
N/A
0x03 <31:24> Delta-Freq Tuning Word (DFTW) Delta-Freq Ramp Rate (DFRRW) Frequency Tuning Word No. 0 (FTW0) Phase Offset Word 0 (POW0) Frequency Tuning Word No.1(FTW1) Phase Offset Word 1 (POW1) Frequency Tuning Word No. 2 (FTW2) Phase Offset Word 2 (POW2) Frequency Tuning Word No. 3 (FTW3) Phase Offset Word 3 (POW3) Reserved 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23
Final Closed-Loop Charge Pump Current (see Table 8)
0x00
N/A
0x01
0x02
0x03
0x04
Not Used
0x05
0x06
Not Used
0x07
0x08
Not Used
0x09
0x0A 0x0B
Not Used
Delta Frequency Word <7:0> Delta Frequency Word <15:8> Delta Frequency Word <23:16> Delta Frequency Word <31:24> Delta Frequency Ramp Rate Word <7:0> Delta Frequency Ramp Rate Word <15:8> Frequency Tuning Word No. 0 <7:0> Frequency Tuning Word No. 0 <15:8> Frequency Tuning Word No. 0 <23:16> Frequency Tuning Word No. 0 <31:24> Phase Offset Word No. 0 <7:0> Not Used Phase Offset Word No. 0 <13:8> Frequency Tuning Word No. 1 <7:0> Frequency Tuning Word No. 1 <15:8> Frequency Tuning Word No. 1 <23:16> Frequency Tuning Word No. 1 <31:24> Phase Offset Word No. 1 <7:0> Not Used Phase Offset Word No. 1 <13:8> Frequency Tuning Word No. 2 <7:0> Frequency Tuning Word No. 2 <15:8> Frequency Tuning Word No. 2 <23:16> Frequency Tuning Word No. 2 <31:24> Phase Offset Word No. 2 <7:0> Not Used Phase Offset Word No. 2 <13:8> Frequency Tuning Word No. 3 <7:0> Frequency Tuning Word No. 3 <15:8> Frequency Tuning Word No. 3 <23:16> Frequency Tuning Word No. 3 <31:24> Phase Offset Word No. 3 <7:0> Not Used Phase Offset Word No. 3 <13:8> Reserved, Do Not Write, Leave at 0xFF Reserved, Do Not Write, Leave at 0xFF
- - - - - - 0x00 0x00 0x00 0x00 0x00 0x00 - - - - - - - - - - - - - - - - - - 0xFF 0xFF
N/A N/A N/A N/A N/A N/A 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 N/A N/A
Rev. A | Page 24 of 32
AD9858
Register Bit Descriptions
Control Function Register (CFR) CFR<26:24>: Wide Closed-Loop Charge Pump Output Current
The CFR is comprised of four bytes located in parallel addresses 0x03 to 0x00. The CFR is used to control the various functions, features, and modes of the AD9858. The functionality of each bit is detailed below. Note that the register bits are identified according to their serial register bit locations beginning with the most significant bit.
CFR<31:30>: Frequency-Detect Mode Charge Pump Current
These bits are used to set the scale factor for the wide closedloop charge pump output current, see Table 9. The charge pump delivers the scaled output current when the control logic forces the charge pump into its wide closed-loop operating mode.
Table 9.
CFR<26:24> 000b 001b 010b 011b 100b 101b 110b 111b Wide Closed-Loop CP Scale Value 0 2 4 6 8 10 12 14 Notes IOUT = 0 (Default) IOUT = 2 x ICP0 IOUT = 4 x ICP0 IOUT = 6 x ICP0 IOUT = 8 x ICP0 IOUT = 10 x ICP0 IOUT = 12 x ICP0 IOUT = 14 x ICP0
These bits are used to set the scale factor for the frequencydetect mode charge pump output current per Table 7. The charge pump delivers the scaled output current when the control logic forces the charge pump into its frequency detect operating mode. The charge pump's baseline output current (ICP0) is determined by the external CPISET resistor and is given by
I CP0 = 1.24/CPISE T
CFR<23>: AutoClear Frequency Accumulator Bit
The recommended nominal value of the CPISET resistor is 2.4 k, which yields a baseline current of 500 A.
Table 7.
Frequency-Detect Charge Pump Scale Value 0 2 3 4
When CFR<23> = 0 (default), a new delta frequency word is applied to the input of the accumulator and added to the currently stored value. When CFR<23> = 1, this bit automatically synchronously clears (loads zeros into) the frequency accumulator for one cycle upon reception of the FUD sequence indicator.
CFR<22>: AutoClear Phase Accumulator Bit
CFR<31:30> 00b 01b 10b 11b
Notes IOUT = 0 (Default) IOUT = 20 x ICP0 IOUT = 40 x ICP0 IOUT = 60 x ICP0
CFR<29:27>: Final Closed-Loop Mode Charge Pump Output Current
When CFR<22> = 0 (default), a new frequency tuning word is applied to the input of the phase accumulator and added to the currently stored value. When CFR<22> = 1, this bit automatically synchronously clears (loads zeros into) the phase accumulator for one cycle upon reception of the FUD sequence indicator.
CFR<21>: Load Delta-Frequency Timer
These bits are used to set the scale factor for the final closedloop mode charge pump output current per Table 8. The charge pump delivers the scaled output current when the control logic forces the charge pump into its final closed-loop mode.
Table 8.
CFR<29:27> 0xxb 100b 101b 110b 111b Final Closed-Loop CP Scale Value 0 1 2 3 4 Notes IOUT = 0 (Default) IOUT = ICP0 IOUT = 2 x ICP0 IOUT = 3 x ICP0 IOUT = 4 x ICP0
When CFR<21> = 1 (default), the contents of the delta frequency ramp rate word are loaded into the ramp rate timer (down counter) upon detection of a FUD sequence. When CFR<21> = 0, the contents of the delta frequency ramp rate word are loaded into the ramp rate timer upon timeout with no regard to the state of the FUD sequence indicator (i.e., the FUD sequence indicator is ignored).
CFR<20>: Clear Frequency Accumulator Bit
When CFR<20> = 1, the frequency accumulator is synchronously cleared and is held clear until CFR<20> is returned to a Logic 0 state (default).
Rev. A | Page 25 of 32
AD9858
CFR<19>: Clear Phase Accumulator Bit Table 10.
CFR<12:11> 00b 01b 1xb Phase Detector Divider Ratio (N) 1 2 4 Notes Default Value LSB Ignored
When CFR<19> = 1, the phase accumulator is synchronously cleared and is held clear until CFR<19> is returned to a Logic 0 state (default).
CFR<18>: Not Used. CFR<17>: PLL Fast-Lock Enable Bit
When CFR<17> = 0 (default), the PLL's fast-lock algorithm is disabled. When CFR<17> = 1, the PLL's fast-lock algorithm is active.
CFR<16>
CFR<10>: Charge Pump Polarity Select Bit
This bit allows the user to control whether or not the PLL's fastlocking algorithm uses the tuning word value to determine whether or not to enter fast-locking mode. When CFR<16> = 0 (default), the PLL's fast-locking algorithm considers the relationship between the programmed frequency tuning word and the instantaneous frequency as part of the locking process. When CFR<16> = 1, the PLL's fast-locking algorithm does not use the frequency tuning word as part of the locking process.
CFR<15>: Frequency Sweep Enable Bit
When CFR<10> = 0 (default), the charge pump is set up for operation with a ground-referenced VCO. In this mode, the charge pump sources current when the frequency at PDIN is less than the frequency at DIVIN. It sinks current when the opposite is true. When CFR<10> = 1, the charge pump is set up for a supplyreferenced VCO. In this mode, the charge pump's source/sink operation is opposite that for a ground-referenced VCO.
CFR<9:8>: Phase Detector Feedback Input Frequency Divider Ratio
These bits set the phase detector divide value per Table 11.
Table 11.
CFR<9:8> 00b 01b 1xb Phase Detector Divider Ratio (M) 1 2 4 Notes Default value LSB ignored
When CFR<15> = 0 (default), the device is in the singletone mode. When CFR<15> = 1, the device is in the frequencysweep mode.
CFR<14>: Sine/Cosine Select Bit
CFR<7>: Not Used CFR<6>: Disable Bit for the 2 GHz REFCLK Divider
When CFR<14> = 0 (default), the angle-to-amplitude conversion logic employs a cosine function. When CFR<14> = 1, the angle-to-amplitude conversion logic employs a sine function.
CFR<13>: Charge Pump Current Offset Bit
When CFR<6> = 0 (default), the REFCLK divide-by-2 function is not bypassed. REFCLK input can be up to 2 GHz. When CFR<6> = 1, the REFCLK divide-by-2 function is disabled. REFCLK input must be no more than 1 GHz.
CFR<5>: SYNCLK Disable Bit
When CFR<13> = 0 (default), the charge pump operates with normal current settings. When CFR<13> = 1, the charge pump operates with offset current settings (see charge pump description).
CFR<12:11>: Phase Detector Reference Input Frequency Divider Ratio
When CFR<5> = 0 (default), the SYNCLK pin is active. When CFR<5> = 1, the SYNCLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is shut down to keep noise generated by the digital circuitry at a minimum. However, the synchronization circuitry remains active (internally) to maintain normal device timing.
CFR<4:2>: Power-Down Bits
These bits set the phase detector divide value per Table 10.
Active high (Logic 1) powers down the respective function. Writing a Logic 1 to all three bits causes the device to enter fullsleep mode. CFR<4> is used to shut down the analog mixer stage (default = 1).
Rev. A | Page 26 of 32
AD9858
CFR<3> is used to shut down the phase detector and charge pump circuitry (default = 1). CFR<2> is used to shut down the DDS core and DAC and to stop all internal clocks except SYNCLK (default = 0).
CFR<1>: SDIO Input Only
As shown in Table 6, the most significant byte of the DFRRW is located in parallel register address 0x09 and the least significant byte at address 0x08.
User Profile Registers
The user profile registers are comprised of the four frequency tuning words and four phase adjustment words. Each pair of frequency and phase registers forms a configurable user profile, selected by the user profile pins.
User Profiles
When CFR<1> = 0 (default), the SDIO pin has bidirectional operation (2-wire serial programming mode). When CFR<1> = 1, the serial data I/O pin (SDIO) is configured as an input only pin (3-wire serial programming mode).
CFR<0>: LSB First
Note that this bit has an effect on device operation only if the I/O port is configured as a serial port. When CFR<0> = 0 (default), MSB first format is active. When CFR<0> = 1, LSB first format is active.
The AD9858 features four user profiles (0-3), selected by profile select pins (PS0, PS1) on the device. Each profile has its own frequency tuning word. This allows the user to load a different frequency tuning word into each profile, which can then be selected as desired by the profile select pins. This makes it possible to hop among the different frequencies at rates up to 1/8 of the SYSCLK while in the single-tone mode. The AD9858 also provides a 14-bit phase-offset word (POW) for each profile. The value in this register is a 14-bit unsigned number (POW) that represents the proportional (PO/214) phase offset to be added to the instantaneous phase value. This allows the phase of the output signal to be adjusted in fine increments of phase (about 0.022). It is possible to update the FTW and POW of any profile while the AD9858 is operating at the frequency specified by another profile and then switch to the profile containing the newly loaded frequency. Changing the current profile updates both parameters so care must be taken to ensure that no unwanted parameter changes take place. It is also possible to repeatedly write a new frequency into the FTW register of a selected profile and to jump to the new frequency by strobing the frequency update pin (FUD). This allows hopping to arbitrary frequencies but is limited in the rate at which this can be accomplished by the speed of the I/O port (100 MHz in parallel mode) and the necessity to transfer several bytes of data for each new frequency tuning word. This can be accomplished rapidly enough for many applications.
Frequency Tuning Control
Other Registers
Delta-Frequency Tuning Word (DFTW)
The DFTW register is comprised of four bytes located in parallel addresses 0x04 to 0x07. The contents of the DFTW are applied to the input of the frequency accumulator. Unlike the frequency tuning word associated with the phase register (which is a 32-bit unsigned integer), the DTFW is a 32-bit signed integer. Because it controls the rate of change of frequency, which can either be a positive or negative value, the DTFW is by definition a signed number. When the device is in the frequency-sweep mode, the output of the frequency accumulator is added to the frequency tuning word and fed to the phase accumulator. This provides the frequency sweep capability of the AD9858. The DFTW controls the frequency resolution associated with a frequency sweep. As shown in Table 6, the most significant byte of the delta frequency tuning word is located in parallel register address 0x07. The lesser significant bytes appear in descending order at parallel register addresses 0x06, 0x05, and 0x04.
Delta-Frequency Ramp Rate Word (DFRRW)
The DFRRW is comprised of two bytes located in parallel addresses 0x08 to 0x09. The DFRRW is a 16-bit unsigned number that serves as a divider for the timer used to clock the frequency accumulator. The timer runs at the DDS CLK rate and generates a clock tick to the frequency accumulator. The number stored in the DFRRW register determines the number of DDS CLK cycles between subsequent ticks to the frequency accumulator. Effectively, the DFRRW controls the rate at which the DFTW is accumulated.
The output frequency of the DDS is determined by the 32-bit frequency tuning word (FTW) and the system clock (SYSCLK). The relationship is described in the following equation
FO =
(FTW x SYSCLK )
2N
where for the AD9858 N = 32. In single-tone mode, the FTW is supplied by the active profile. In frequency-sweeping mode, the FTW is the output of the frequency accumulator.
Rev. A | Page 27 of 32
AD9858
Phase Offset Control
A 14-bit phase offset () may be added to the output of the phase accumulator by means of the phase offset words stored in the memory registers. This feature provides the user with three different methods of phase control. The first method is a static phase adjustment, where a fixed phase offset is loaded into the appropriate phase-offset register and left unchanged. The result is that the output signal is offset by a constant angle relative to the nominal signal. This allows the user to phase align the DDS output with an external signal, if necessary. The second method of phase control is where the user regularly updates the appropriate phase-offset register via the I/O port. By properly modifying the phase offset as a function of time, the user can implement a phase modulated output signal. The rate at which phase modulation can be performed is limited by both the speed of the I/O port and the frequency of SYSCLK. The third method of phase control involves the profile registers, in which the user loads up to four different phase-offset values into the appropriate profiles. The user can then select among the four preloaded phase-offset values via the AD9858 profile select pins. Thus, the phase changes are accomplished by driving the hardware pins rather than writing to the I/O port, thereby avoiding the speed limitation imposed by the I/O port. However, this method is restricted to only four phase-offset values (one phase-offset value per profile). Each profile has an associated frequency and phase value. Changing the current profile updates both parameters, so care must be taken to ensure that no unwanted parameter changes take place. Note that the phase-offset value is routed through a unit delay (z-1) block. This is done to ensure that updates of the phaseoffset values exhibit the same amount of latency as updates of the frequency tuning word. Otherwise, if the user decides to update both frequency and phase-offset values, the phase-offset
change would propagate through the device before the tuning word change. The presence of the unit delay in the phase-offset path ensures that both frequency and phase-offset changes exhibit similar latency.
Profile Selection
A profile consists of a specific group of memory registers (see Table 6). In the AD9858 each profile contains a 32-bit frequency tuning word and a 14-bit phase-offset word. Each profile is selectable via two external profile select pins (PS0 and PS1) as defined in Table 12. The specific mapping of registers to profiles is detailed in the Register Bit Descriptions section. The user should be aware that selection of a profile is internally synchronized with DDS CLK using the SYNCLK timing. That is, SYNCLK is used to synchronize the assertion of the profile select pins (PS0, PS1). Therefore, the PS0 and PS1 pins must be set up and held around the rising edge of SYNCLK. The PS0 and PS1 inputs are designed for zero hold time and 3.5 ns setup time.
Table 12.
PS1
0 0 1 1
PS0
0 1 0 1
Profile
0 1 2 3
The profiles are available to the user to provide rapid changing of device parameters via external hardware, which alleviates the speed limitations imposed by the I/O port. For example, the user might preprogram the four phase offset registers with values that correspond to phase increments of 90. By controlling the PS0 and PS1 pins, the user can implement /2 phase modulation. The data modulation rate would be much higher than that possible by repeatedly reloading a single phaseoffset register via the I/O port.
Rev. A | Page 28 of 32
AD9858
AD9858 APPLICATION SUGGESTIONS
FREQUENCY TUNING WORD
DC-400MHz
FREF DC-150MHz PHASE/ FREQUENCY DETECTOR 150MHz CHARGE PUMP 0.5mA-2mA (0.5mA STEPS) PLL LOOP FILTER VCO
32
DDS 1000MSPS
10
DAC FILTER
DIVIDER 1/2/4
DDS/DAC CLOCK 1000MHz ANALOG MIXER DIVIDER 1/2
2GHz 150MHz
AD9858
2GHz FILTER 2GHz FIXED LOOP (LO1)
03166-A-040
Figure 37. DDS Synthesizer Translation Loop Oscillator (Implemented in Translation Loop Evaluation Board)
FREQUENCY TUNING WORD
DC-400MHz
FREF DC-150MHz PHASE/ FREQUENCY DETECTOR 150MHz CHARGE PUMP 0.5mA-2mA (0.5mA STEPS) VCO LOOP FILTER F = MxFREF
32
DDS 1000MSPS
10
DAC FILTER
DIVIDER 1/2/4
DDS/DAC CLOCK
DIVIDER
Figure 38. DDS Synthesizer Single-Loop PLL Up-Conversion
150MHz REFERENCE
DIVIDER 1/2/4
PHASE/ FREQUENCY DETECTOR 150MHz
CHARGE PUMP 0.5mA-2mA (0.5mA STEPS)
VCO LOOP FILTER
150MHz
AD9858
DAC FILTER DDS 1000MSPS 32 FREQUENCY TUNING WORD 1000 MHz DIVIDER 1/2 2GHz MAX
Figure 39. DDS Synthesizer AD9858 as Fractional N Synthesizer (Implemented in Fractional Divide Evaluation Board)
Rev. A | Page 29 of 32
03166-A-042
03166-A-041
AD9858
AD9858
EVALUATION BOARDS
The AD9858 has three different evaluation board designs. The first design is the traditional DDS evaluation board. In this design, the DDS is clocked and the output is taken directly from the DAC. The analog mixer and PLL blocks are made available for separate evaluation. The second design is a fractional-divide loop. This evaluation board was designed to incorporate the DDS, the phase-detector, and the charge pump. In this application, the DDS is used in a PLL loop. Unlike a fixed divider used in traditional PLL loops, the output signal is divided and fed back to the phase detector by the DDS. To do this, the output signal of the PLL loop is fed to the DDS as REFCLK. The DDS is programmed to match the reference input frequency. Because the DDS output frequency can take on 232 potential values between 0 Hz and one half of the PLL loop output frequency, this enables frequency resolution on the order of 470 MHz, assuming a PLL loop output frequency of 2 GHz. The third design is a translation loop or offset loop. In this design, the RF mixer is incorporated into the feedback path of the loop. This allows direct up-conversion to the transmission frequency. The three evaluation boards have separate schematics, BOMS, and instructions. See www.analog.com/dds for more information.
Table 13.
Part Number AD9858PCB AD9858FDPCB AD9858TLPCB Description AD9858 Frequency Synthesizer Board AD9858 Fractional-Divide Loop Frequency Synthesizer Board AD9858 Translation Loop Frequency Synthesizer Board
Rev. A | Page 30 of 32
AD9858 OUTLINE DIMENSIONS
0.75 0.60 0.45 SEATING PLANE 1.20 MAX
100 1
16.00 SQ 14.00 SQ
76 75 76 75 100 1
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
9.50 SQ
0.20 0.09
25 26
50 49
50 49 26
25
7 3.5 0
0.50 BSC 0.27 0.22 0.17
1.05 1.00 0.95
0.15 0.05
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
Figure 40. 100-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/EP] (SV-100) Dimensions shown in millimeters
WARNING
EPAD (thermal slug) must be attached to ground plane for some other large metal mass for thermal transfer. Failure to do so may cause excessive die temperature rise and damage to the device.
ORDERING GUIDE
Models AD9858BSV AD9858PCB AD9858FDPCB AD9858TLPCB Temperature Range -40C to +85C 25C 25C 25C Package Description 100-Lead EPAD Generic Evaluation Board Fractional-Divide Evaluation Board Translation Loop Evaluation Board Package Option SV-100
Rev. A | Page 31 of 32
AD9858 NOTES
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03166-0-11/03(A)
Rev. A | Page 32 of 32

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